1. Field of the Invention
This invention relates to a synchronous semiconductor memory device which operates in synchronization with a clock, and particularly relates to a synchronous semiconductor memory device having a configuration for controlling operation timings corresponding to a latency after an issuance of a command for various purposes.
2. Description of the related art
Recently SDRAM (Synchronous Dynamic Random Access Memory) of DDR (Double Data Rate) type has been a mainstream as a synchronous semiconductor memory device to allow high speed operation. Since this DDR-SDRAM (referred to as DDR-SDRAM hereinafter) employs a high speed clock, a considerable number of clock cycles are required between issuing a command and completion of a data transmission in read/write operation. Therefore, a configuration is employed in which a predetermined number of clock cycles of an external clock is preliminarily set as a latency based on operation of the DDR-SDRAM and a latency counter is provided to count the set latency based on an internal clock (for example JP-A-2002-230973). In the DDR-SDRM, different latencies are defined for various types of operation and users can preset a desired latency in a mode register. Further, with progress of the DDR-SDRAM generation, speed of the external clock increases and the required latency tends to gradually increase. Under the circumstances, a configuration of the latency counter of the DDR-SDRAM is required, in which the number of clock cycles can be counted in a wide range and selectively output.
FIG. 11 shows an example of a configuration of the latency counter applied to the above mentioned conventional DDR-SDRAM. FIG. 12 shows operation waveforms at each part of the latency counter of FIG. 11. The latency counter shown in FIG. 11 is composed of D flip flops (D-F/F) 101 to 109 functioning as a shift register of nine stages, selectors 110 and 111, an OR circuit 112, and a D flip flop 113 on the output side. Shifting operation of each of the D flip flops 101 to 109 and 113 is controlled at rising edges of an internal clock PCLK. This internal clock PCLK is generated based on the external clock having a period tCK and has the same period tCK.
In the first stage D flip flop 101, a command signal COM output from a command decoder is input when a predetermined external command is input. As shown in FIG. 12, the command signal COM is a pulse which rises with slight delay from first cycle T0 at which the external command is captured. A signal F1 to which the command signal COM is shifted one period tCK is output from the first stage D flip-flop 101 and is input to the second D flip-flop 102 in a period of cycle T1. Similarly, signals F2 to F9 to which the command signal COM shifted one by one period tCK in order are output from the D flip flops 102 to 109 of the second to ninth stages and are input to the subsequent stages in periods of cycles T2 to T9 sequentially.
The signals F2 to F5 of the D flip flops 102 to 105 of the second to fifth stages are input to the selector 110. The signals F6 to F9 of the D flip flops 106 to 109 of the sixth to ninth stages are input to the selector 111. A control signal Ca is input to a selector 31 and a control signal Cb is input to a selector 32, each of which functions as a control signal for selecting a predetermined latency. One of eight signals F2 to F9 is selected and output in response to these control signals Ca and Cb. Controls for selecting one of the eight signals F2 to F9 corresponds to settings of latencies 4 to 11 respectively.
In the example of FIG. 12, a case is shown in which the signal F5 of the fifth stage D flip flop 105 is selected and output by the selector 110 corresponding to a setting of latency 7. Therefore, the signal F5 is input to the OR circuit 112 from the D flip flop 105 through the selector 110, and a signal OR is output from the OR circuit 112. The signal OR which rises in the period of cycle T5 is input to the D flip flop 113 on the output side to be shifted one period tCK, and a signal Sout which rises in the period of cycle T6 is output. This signal Sout is output to the next stage circuit, and a latency equivalent to 7tCK from cycle T0 to cycle T7 can be counted by controlling using a rising edge of the subsequent cycle T7.
In FIG. 11, in cases of counting different latencies, basic operations are the same. When the minimum latency 4 is set, the signal F2 of the second stage D flip flop 102 is selected and output by the selector 110, and a latency equivalent to 4tCK from cycle T0 to cycle T4 is counted. When the maximum latency 11 is set, the signal F9 of the final stage D flip flop 109 is selected and output by the selector 111, and a latency equivalent to 11tCK from cycle T0 to cycle T11 is counted.
However, in the above-mentioned operation of the conventional latency counter, since an operation frequency of the D flip flops 101 to 109 conforms to the external clock frequency, consumption current of the nine-stage shift register increases. That is, since the internal clock having the same frequency as the external clock is applied to each stage of the nine-stage shift register, sequential shift operation of each stage performed at every period tCK of the external clock causes a problem of an increase in the entire consumption current. In this case, it is a problem that as the speed of the external clock increases, the consumption current rapidly increases. And since the minimum period tCKmin of the external clock is restricted by circuit operation such as transfer speed of the shift register, sufficient operation margin can not be secured, which may also cause a problem of high speed.